Trench isolation and method of fabricating trench isolation

ABSTRACT

Trench isolation structure and method of forming trench isolation structures. The structures includes a trench in a silicon region of a substrate, the trench extending from a top surface of the substrate into the silicon region; an ion implantation stopping layer over sidewalls of the trench; a dielectric fill material filling remaining space in the trench, the dielectric fill material not including any materials found in the stopping layer; an N-type dopant species in a first region of the silicon region on a first side of the trench; the N-type dopant species in a first region of the dielectric material adjacent to the first side of the trench; a P-type dopant species in a second region of the silicon region on a second side of the trench; and the P-type dopant species in a second region of the dielectric material adjacent to the second side of the trench.

RELATED APPLICATIONS

The present application is division of U.S. patent application Ser. No.13/192,561 filed on Jul. 28, 2011 which is a division of U.S. patentapplication Ser. No. 11/839,585 filed Aug. 16, 2007.

FIELD OF THE INVENTION

The present invention relates to the field of integrated circuits andmethod of fabricating integrated circuits; more specifically, it relatesto a trench isolation structure of integrated circuits and method offabricating trench isolation during integrated circuit manufacture.

BACKGROUND OF THE INVENTION

Complementary metal-oxide-silicon (CMOS) based integrated circuitsutilize p-channel field effect transistors (PFETs) and n-channel fieldeffect transistors (NFETs). Many integrated circuit designs require thedevices (i.e., the PFETs and NFETs) to be placed adjacent to each other,which is accomplished by isolating the PFETs and NFETs with trenchisolation. Trench isolation is essentially a dielectric filled trenchformed in the silicon substrate that surrounds the perimeter of andelectrically isolates the regions of the PFETs and NFETs formed in thesilicon substrate from each other.

However, with the ever increasing need for increased device density, thewidth of the trench isolation between adjacent devices is decreasing anddefect free isolation structures are becoming more difficult tofabricate. Accordingly, there exists a need in the art to improve thetrench isolation structure and fabrication methodologies to keep pacewith the decreasing dimensions of the trench isolation.

SUMMARY OF THE INVENTION

A first aspect of the present invention is a method, comprising: (a)forming a trench in a silicon region of a substrate, the silicon regionadjacent to a top surface of the substrate, the trench extending fromthe top surface of the substrate into the silicon region; (b) forming astopping layer on sidewalls and a bottom of the trench; (c) removing thestopping layer from the bottom of the trench; (d) filling remainingspace in the trench with a dielectric fill material, the dielectric fillmaterial not including any materials found in the stopping layer; (e)performing an N-type ion implantation on a first side of the trench intoa first region of the silicon region abutting the first side of thetrench and into a first region of the dielectric material abutting thestopping layer on the first side of the trench; and (f) performing aP-type ion implantation on an second side of the trench into a secondregion of the silicon region abutting the second side of the trench andinto a second region of the dielectric material abutting the stoppinglayer on the second side of the trench, the second side of the trenchopposite the first side of the trench.

A second aspect of the present invention is a method comprising: (a)forming a trench in a silicon region of a substrate, the silicon regionadjacent to a top surface of the substrate, the trench extending fromthe top surface of the substrate into the silicon region; (b) forming aninsulating layer on sidewalls and a bottom of the trench; (c) forming astopping layer on the insulating layer; (d) filling remaining space inthe trench with a dielectric fill material, the dielectric fill materialnot including any materials found in the stopping layer; (e) performingan N-type ion implantation on a first side of the trench into a firstregion of the silicon region abutting the first side of the trench andinto a first region of the dielectric material abutting the insulatinglayer on the first side of the trench; and (f) performing a P-type ionimplantation on an second side of the trench into a second region of thesilicon region abutting the second side of the trench and into a secondregion of the dielectric material abutting the stopping layer on thesecond side of the trench, the second side of the trench opposite thefirst side of the trench.

A third aspect of the present invention is a structure, comprising: atrench in a silicon region of a substrate, the silicon region adjacentto a top surface of the substrate, the trench extending from the topsurface of the substrate into the silicon region; a stopping layer oversidewalls of the trench; a dielectric fill material filling remainingspace in the trench, the dielectric fill material not including anymaterials found in the stopping layer; an N-type dopant species in afirst region of the silicon region on a first side of the trench; theN-type dopant species in a first region of the dielectric materialadjacent to the first side of the trench; a P-type dopant species in asecond region of the silicon region on a second side of the trench, thesecond side of the trench opposite the first side of the trench; and theP-type dopant species in a second region of the dielectric materialadjacent to the second side of the trench.

BRIEF DESCRIPTION OF THE DRAWINGS

The features of the invention are set forth in the appended claims. Theinvention itself, however, will be best understood by reference to thefollowing detailed description of an illustrative embodiment when readin conjunction with the accompanying drawings, wherein:

FIG. 1A is a top view and FIG. 1B is a cross-sectional view through line1B-1B of FIG. 1A illustrating a defect mechanism related to thedecreasing the width of trench isolation;

FIGS. 2A through 2J are cross-sectional drawings illustratingfabrication of trench isolation and device structures according to afirst embodiment of the present invention;

FIGS. 3A through 3C are cross-sectional drawings illustratingfabrication of trench isolation and device structures according to asecond embodiment of the present invention;

FIGS. 4A and 4B are cross-sectional drawings illustrating fabrication oftrench isolation and device structures according to a third embodimentof the present invention; and

FIGS. 5A through 5C are cross-sectional drawings illustratingfabrication of trench isolation and device structures according to afourth embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1A is a top view and FIG. 1B is a cross-sectional view through line1B-1B of FIG. 1A illustrating a defect mechanism related to thedecreasing width of the trench isolation. In FIGS. 1A and 1B, asemiconductor substrate 100 includes an N-well region 105 and a P-wellregion 110 separated by dielectric trench isolation 115. Note N-well 105and P-well 110 abut under trench isolation 115. Formed on a top surface120 of substrate 100 is a gate dielectric layer 125 and formed on a topsurface 130 of the gate dielectric layer is an electrically conductivegate electrode 135.

A PFET 145 is formed in N-well 105. PFET 145 includes first and secondsource/drain 150A and 150B formed in N-well 105 on opposite sides ofgate electrode 135 and first and second source/drain extensions 155A and155B formed in the N-well under opposite edges of the gate electrode.First and second source/drains 155A and 155B abut trench isolation 115and extend from top surface 120 of substrate 100 into N-well 105, butnot through the bottom of the N-well. First and second source/drainextensions 155A and 155B abut trench isolation 115 and abut first andsecond source/drains 150A and 150B and extend from top surface 120 ofsubstrate 100 into N-well 105, but not as far into the N-well as firstand second source/drains 155A and 155B. First and second source/drains155A and 155B and first and second source/drain extensions 155A and 155Bare doped P-type. N-well 105 is doped N-type and forms the channelregion of PFET 145.

An NFET 160 is formed in N-well 105. NFET 160 includes first and secondsource/drain 165A and 165B formed in P-well 110 on opposite sides ofgate electrode 135 and first and second source/drain extensions 170A and170B formed in the P-well under opposite edges of the gate electrode.First and second source/drains 170A and 170B abut trench isolation 115and extend from top surface 120 of substrate 100 into P-well 110, butnot through the bottom of the P-well. First and second source/drainextensions 170A and 170B abut trench isolation 115 and abut first andsecond source/drains 165A and 165B and extend from top surface 120 ofsubstrate 100 into P-well 110, but not as far into the P-well as firstand second source/drains 170A and 170B. First and second source/drains170A and 170B and first and second source/drain extensions 170A and 170Bare doped N-type. P-well 110 is doped P-type and forms the channelregion of NFET 160.

Generally, N-well 105 and P-well 115 are formed by separateion-implantations of dopant species through respective blocking layerswhose edges overlay an already formed trench isolation 115. However,ion-implantation is subject to straggle. Straggle is the deflection ofimplanted species from their original trajectories as they penetrateinto the target material, in the present case, N-well 105 and trenchisolation 115 or P-well 110 and trench isolation 115. If the width oftrench isolation 115 between N-well and P-well 110 is too small, thenP-type regions 140A can form along the edges of the trench isolation inN-well 105 due to straggle of the P-well implant in trench isolation 115and N-type regions 140B can form along the edges of the trench isolationin P-well 110 due to straggle of the N-well implant in trench isolation115. P-type regions 140A can cause leakage between the first and secondsource/drains 150A and 150B of PFET 145 and N-type regions 140A cancause leakage between the first and second source/drains 165A and 165Bof NFET 160.

The defect mechanism (regions 140A and 140B) illustrated in FIGS. 1A and1B and described supra, were discovered by the inventors by studiesrelated to measurement of NFET leakage currents that behaved asdepletion layer punch through, but only for NFET devices proximate toPFET devices, and was found to track with certain of the N-wellion-implantation doses and was confirmed by running simulation models.

FIGS. 2A through 2J are cross-sectional drawings illustratingfabrication of trench isolation and device structures according to afirst embodiment of the present invention. In FIG. 1A, formed on a topsurface 195 of a substrate 200 is a pad later 205. Pad layer 205 acts asan etch stop layer, a polish stop layer and a hardmask layer. Pad layer205 may comprise multiple layers. In one example, substrate 200 issingle-crystal silicon. In one example, pad layer 205 comprises a layerof silicon nitride over a layer of silicon dioxide, the silicon dioxidecontacting substrate 200.

In FIG. 2B an opening 210 is formed in pad layer 210 to expose topsurface 195 of substrate 200 in the opening. Opening 200 is in thepattern of the trench isolation required for the integrated circuitbeing fabricated. Opening 210 may be formed photolithographically by (1)forming a photoresist layer on top of the pad layer, (2) exposing thephotoresist layer to actinic radiation through a patterned photomask,(3) developing the photoresist layer to transfer the pattern of thephotomask into the photoresist layer, (4) etching (e.g., reactive ionetching (RIE)) though the pad layer not protected by the patternedphotoresist layer, (5) removing the photoresist layer.

In FIG. 2C, a trench 215 is etched into substrate 200 through opening210 in pad layer 205. Trench 215 has a depth D and a width W (where anN-well and a P-Well will be subsequently formed). In one example, trench215 is formed by a RIE process. In one example D is less than about 350nm and W is less than about 120 nm. In one example the ratio of D/W isequal to or greater than 3.

In FIG. 2D, a stopping layer 220 is conformally formed over top surface225 of pad layer 205 and the sides 230 and bottom 235 of trench 215.Stopping layer 220 comprises a material with a high ion implantationstopping power (e.g., is of sufficient density to prevent ions of P andN type dopant species to be later ion-implanted into the then filledtrench 215 from penetrating into substrate 200 through stopping layer220 on sidewalls 230 of trench 215). Stopping power is a measure of thethickness of a given layer of material needed to stop 100% of the ionsimplanted into the layer within the layer. Calculations of stoppingpower can be complex, but to a first order, stopping power is related tothe density of the material of the layer. Stopping layer 220 is adielectric material. Examples of suitable materials for stopping layer220 include but are not limited to aluminum oxide (Al₂O₃), siliconcarbide, hafnium oxide (HfO₂) hafnium carbide, hafnium silicate(HfSi_(x)O_(y)), tantalum oxide (Ta₂O₅), zirconium oxide (ZrO₂) andcombinations thereof. In one example the density of stopping layer 220is greater than about 3 grams/cm³, preferably greater than about 8grams/cm³. Stopping layer 220 cannot be silicon dioxide or siliconnitride and are specifically excluded. In one example the thickness ofstopping layer 220 is between about 20 nm and about 75 nm. In oneexample, the thickness of stopping layer 220 is no greater than (W/4)see FIG. 2C. In one example, the thickness of stopping layer 220 isselected based on the density of the material of the stopping layer andthe ion implant energy (e.g., KeV) of the implanted species.

In FIG. 2E, etch stop later 220 (see FIG. 2D) has been removed from topsurface 225 of pad layer 205 and bottom 235 of trench 215 to formsidewall liner 230 on the sides 230 of the trench. This may beaccomplished using an RIE process. In one example, the RIE processetches stopping layer 220 selective to substrate 200 (e.g., selective tosilicon) and/or pad layer 205. (Etching a first layer “selective to” asecond layer means a process that etches the first layer (e.g., stoppinglayer 220) faster than the second layer (e.g., substrate 200 and/or padlayer 205) or not at all. Sidewall liner 230 may also be called“spacers.” While the uppermost edge 242 of sidewall liner 240 are shownco-planar with top surface 225 of pad layer 205, edge 242 may berecessed below top surface 225 or coplanar or recessed below top surface195 of substrate 200. In one example, it is advantageous that nostopping layer 220 (see FIG. 2D) should remain on the bottom 235 oftrench 215, as penetration of the N-well and P-well ion implantsdescribed infra into substrate 200 under trench 215 is desirable in manycases.

In FIG. 2F, a layer of dielectric fill 245 is formed over all exposedsurfaces pad layer 205, sidewall liner 215 and bottom 235 of trench 215.Dielectric fill 245 completely fills the remaining space in trench 215.In one example, dielectric fill 245 is a high density plasma (HDP)silicon dioxide or tetraethoxysilane (TEOS) deposited silicon dioxide.Dielectric fill 245 and stopping layer 220 comprise different materials.In one example, Dielectric fill 245 includes no material found instopping layer 220.

In FIG. 2G, a chemical mechanical polish (CMP) has been performed toform trench isolation 250 comprising sidewall liner 240 and dielectricfill 245. A top surface 252 of trench isolation 250 is coplanar with topsurface 225 of pad layer 205. While edges 242 of sidewall liner 240 isillustrated as coplanar with top surface 225 of pad layer 205, if theedges had been recessed as described supra, then the edges would becovered with dielectric fill 245.

In FIG. 2H, an N-type ion implantation(s) 255 is performed intosubstrate 200 to form an N-well 260A. A patterned photoresist layer 265is formed over portions of substrate 200 where it is not desirable toform N-wells prior to the N-type ion implantation(s). An edge 267 ofphotoresist layer 265 is aligned over dielectric fill 245. Because ofsidewall liner 240, little to none of the N-type dopant speciesimplanted into dielectric fill can “straggle” into substrate 200 underphotoresist layer 265. Formation of patterned photoresist layers hasbeen described supra. After the ion implantation, photoresist layer 265is removed.

A typical N-well ion implantation process includes multipleion-implantations of N-type dopant species at different andprogressively lower voltages. For example, three ion implantations of400 KeV, 250 KeV and 50 KeV at doses in the 10¹² to 10¹³ atom/cm² range.

In FIG. 2I, a P-type ion implantation(s) 270 is performed into substrate200 to form a P-well 260B. A patterned photoresist layer 275 is formedover portions of substrate 200 where it is not desirable to form P-wellsprior to the P-type ion implantation(s). An edge 277 of photoresistlayer 275 is aligned over dielectric fill 245. Because of sidewall liner240, little to none of the P-type dopant species implanted intodielectric fill can “straggle” into substrate 200 under photoresistlayer 275. Formation of patterned photoresist layers has been describedsupra. After the ion implantation, photoresist layer 275 is removed.

A typical P-well ion implantation process includes multipleion-implantations of P-type dopant species at different andprogressively lower voltages. For example, three ion implantations of220 KeV, 120 KeV and 40 KeV at doses in the 10¹² to 10¹³ atom/cm² range.

Note, the P-well ion implantation and related processes may be performedbefore the N-well ion implantation and related processes.

In FIG. 2J, pad layer 275 and PFET and NFET devices are fabricatedincluding gate dielectric layer 125 and gate electrode 135 similar toFIGS. 1A and 1B without the straggle regions 140A and 140B. A simplifiedprocess sequence would include: (1) removing the pad layer, (2) forminga gate dielectric layer, (3) forming gate electrodes, (4) formingsidewall spacers on the sides of the gate electrodes, (5) ion implantingthe NFET source/drains, (6) ion implanting the PFET source/drains, (7)ion implanting the NFET source/drain extensions, (8) ion implanting thePFET source/drain extensions, (9) forming contacts to the NFET and PFETsource/drains and gate electrodes, forming wiring levels to connect theNFETs and PFETs into integrated circuits. The order of the ionimplanting steps 5 through 8 may be changed.

FIGS. 3A through 3C are cross-sectional drawings illustratingfabrication of trench isolation and device structures according to asecond embodiment of the present invention. The second embodiment of thepresent inventions differs from the first embodiment in that it allowsthe use an electrically conductive (e.g., metal) stopping layer. Metalsand electrical conductors generally have greater density and thusstopping power than dielectrics. The steps illustrated in FIGS. 2Athrough 2C and described supra, are performed prior to the processesillustrated in FIG. 3A.

In FIG. 3A, a insulating layer 280 is conformally formed over topsurface 225 of pad layer 205 and the sides 230 and bottom 235 of trench215. In one example, insulating layer 280 comprises silicon dioxide,silicon nitride or another dielectric material. In one example thethickness of insulating layer 280 is between about 20 nm and about 75nm. In one example, the thickness of insulating layer 280 is no greaterthan (W/4) see FIG. 2C.

In FIG. 3B, sidewall liner 285 are formed over insulating layer 280 onsidewalls 230 of trench 215. Sidewall liner 285 may be formed byconformally depositing a layer of liner material and performing a RIE toremove the horizontal portions (relative to top surface 195 of substrate200) of the layer of liner material. Insulating layer 280 preventssidewall liner 285 from shorting to substrate 200. It is advantageousfor uppermost edges 287 of sidewall liner 285 to be recessed below topsurface 195 of substrate 200 to avoid electrical contact to subsequentlyformed gate electrodes. Examples of suitable materials for sidewallliner 285 include but are not limited to nickel, cobalt, copper,chromium, molybdenum, germanium, palladium, silver, hafnium, tungsten,tungsten carbide, tungsten nitride, gold, platinum, and combinationsthereof. In one example the density of sidewall liner 285 is greaterthan about 8 grams/cm³, preferably greater than about 12 grams/cm³. Inone example the thickness of sidewall liner 285 measured in a directionparallel to top surface 195 of substrate 200 is between about 20 nm andabout 75 nm. In one example, the thickness of sidewall liner 285 is nogreater than (W/4) see FIG. 2C.

In FIG. 3C, the processes illustrated in FIGS. 2F and 2G and describedsupra are performed to form trench isolation 250A comprising insulatinglayer 280, sidewall liner 285 and dielectric fill 245. The processesillustrated in FIGS. 2H through 2J and described supra, are nextperformed after the step illustrated in FIG. 3C with an N-well beingformed in region 290A and a P-well being formed in region 290B ofsubstrate 200.

In a variant of the third embodiment of the present invention, stoppinglayer 220 is sufficiently thick to completely fill trench 215 and nodielectric fill 245 is required.

FIGS. 4A and 4B are cross-sectional drawings illustrating fabrication oftrench isolation and device structures according to a third embodimentof the present invention. The third embodiment of the present inventionis similar to the first embodiment of the present invention, except, theprocess has been simplified for use with silicon-on-insulator (SOI)substrates. The steps illustrated in FIGS. 2A through 2C and describedsupra, are performed prior to the step illustrated in FIG. 4A.

In FIG. 4A, an SOI substrate 300 comprises a buried oxide (BOX) layer305 between a lower silicon layer 305 and an upper silicon layer 315.Trench 215 reaches to BOX layer 305 and stopping layer 220 isconformally formed on top of regions of BOX layer 305 exposed in bottom235 of trench 215.

In FIG. 4B, the processes illustrated in FIGS. 2F and 2G and describedsupra are performed to form trench isolation 250B comprising stoppinglayer 220 and dielectric fill 245. The processes illustrated in FIGS. 2Ithrough 2J and described supra, are performed after the processesillustrated in FIG. 4B with an N-well being formed in region 320A and aP-well being formed in region 320B of silicon layer 315. Optionally, theCMP step used to remove excess dielectric fill 245 may remove regions ofblocking layer 220 in contact with top surface 225 of pad layer 205, orthe regions of blocking layer 220 in contact with top surface 225 of padlayer 205 may be removed when pad layer 205 is removed.

FIGS. 5A through 5C are cross-sectional drawings illustratingfabrication of trench isolation and device structures according to afourth embodiment of the present invention. The fourth embodiment of thepresent invention is similar to the second embodiment of the presentinvention, except, the process has been simplified for use with SOIsubstrates. The processes illustrated in FIGS. 2A through 2C anddescribed supra, are performed prior to the step illustrated in FIG. 5A.

In FIG. 5A, trench 215 reaches to BOX layer 305 and insulating layer 220is conformally formed on top of regions of BOX layer 305 exposed inbottom 235 of trench 215. Then stopping layer 285 is conformally formedover insulating layer 280. Insulating layer 280 prevents sidewall liner285 from shorting to silicon layer 315.

In FIG. 5B, sidewall liner 285 are formed over insulating layer 280 onsidewalls 230 of trench 215 as described supra with respect to FIG. 3B.It is advantageous for uppermost edges 287 of sidewall liner 285 to berecessed below top surface 325 of silicon layer 315 to avoid electricalcontact to subsequently formed gate electrodes.

In FIG. 5C, the processes illustrated in FIGS. 2F and 2G and describedsupra are performed to form trench isolation 250C comprising insulatinglayer 280, sidewall liner 285 and dielectric fill 245. The processesillustrated in FIGS. 2I through 2J and described supra, are performedafter the processes illustrated in FIG. 5C with an N-well being formedin region 320A and a P-well being formed in region 320B of silicon layer315. Optionally, the CMP step used to remove excess dielectric fill 245may remove regions of insulating layer 280 in contact with top surface225 of pad layer 205, or the regions of insulating layer 280 in contactwith top surface 225 of pad layer 205 may be removed when pad layer 205is removed.

In a variant of the fourth embodiment of the present invention, stoppinglayer 285 is sufficiently thick to completely fill trench 215 and nodielectric fill 245 is required.

Thus the present invention provides trench isolation structures andfabrication methodologies that allow decreasing dimensions of the trenchisolation.

The description of the embodiments of the present invention is givenabove for the understanding of the present invention. It will beunderstood that the invention is not limited to the particularembodiments described herein, but is capable of various modifications,rearrangements and substitutions as will now become apparent to thoseskilled in the art without departing from the scope of the invention.For example, the first and third embodiments of the present inventionmay be performed on bulk silicon substrates (e.g. substrate 200 of, forexample, FIG. 2A). Therefore, it is intended that the following claimscover all such modifications and changes as fall within the true spiritand scope of the invention.

What is claimed is:
 1. A method, comprising: (a) forming a trench in a silicon region of a substrate, said silicon region adjacent to a top surface of said substrate, said trench extending from said top surface of said substrate into said silicon region; (b) forming a stopping layer on sidewalls and a bottom of said trench; (c) removing said stopping layer from said bottom of said trench; (d) filling remaining space in said trench with a dielectric fill material, said dielectric fill material not including any materials found in said stopping layer; (e) performing an N-type ion implantation on a first side of said trench into a first region of said silicon region abutting said first side of said trench and into a first region of said dielectric material abutting said stopping layer on said first side of said trench; and (f) performing a P-type ion implantation on an second side of said trench into a second region of said silicon region abutting said second side of said trench and into a second region of said dielectric material abutting said stopping layer on said second side of said trench, said second side of said trench opposite said first side of said trench.
 2. The method of claim 1, wherein said stopping layer comprising a material with a density of least 3.0 grams/cm³.
 3. The method of claim 1, wherein said stopping layer comprises a material selected from the group consisting of aluminum oxide, silicon carbide, hafnium oxide hafnium carbide, hafnium silicate tantalum oxide, zirconium oxide and combinations thereof.
 4. The method of claim 1, further including: (g) forming a source and a drain of a PFET in said N-well, said source and said drain of said PFET abutting different regions of said first side of said trench and forming a source and a drain of an NFET in said P-well, said source and said drain of said NFET said abutting different regions of said second side of said trench.
 5. A method, comprising: (a) forming a trench in a silicon region of a substrate, said silicon region adjacent to a top surface of said substrate, said trench extending from said top surface of said substrate into said silicon region; (b) forming an insulating layer on sidewalls and a bottom of said trench; (c) forming a stopping layer on said insulating layer; (d) filling remaining space in said trench with a dielectric fill material, said dielectric fill material not including any materials found in said stopping layer; (e) performing an N-type ion implantation on a first side of said trench into a first region of said silicon region abutting said first side of said trench and into a first region of said dielectric material abutting said insulating layer on said first side of said trench; (f) performing a P-type ion implantation on an second side of said trench into a second region of said silicon region abutting said second side of said trench and into a second region of said dielectric material abutting said stopping layer on said second side of said trench, said second side of said trench opposite said first side of said trench; and, between steps (c) and (d), removing said stopping layer from regions of said insulating layer in said bottom of said trench to expose said insulating layer in said bottom of said trench, said stopping layer remaining on regions of said insulating layer that are on said sidewalls of said trench.
 6. The method of claim 5, wherein said stopping layer comprises a material with a density of least 8.0 grams/cm³.
 7. The method of claim 5, wherein said stopping layer comprises a material selected from the group consisting of nickel, cobalt, copper, chromium, molybdenum, germanium, palladium, silver, hafnium, tungsten, tungsten carbide, tungsten nitride, gold, platinum, and combinations thereof.
 8. The method of claim 5, further including: (g) forming a source and a drain of a PFET in said first region of said silicon region, said source and said drain of a PFET said abutting different regions of said first side of said trench; and (h) forming source/drains of an NFET in said second region of said silicon region, said source and said drain of a PFET said abutting different regions of said first side of said trench. 